1. Technical Field
The present disclosure relates to analog/digital (A/D) converters and, in particular, to a high-speed voltage following device for conversion systems of the analog/digital type (hereinafter, for the sake of brevity, A/D conversion systems).
2. Description of the Related Art
With reference to FIG. 1, a system 100 for A/D conversion of an electric signal is typically composed of a sampling network RCM, for example, a capacitive input stage of the “Sample and Hold” type, per se known, for the sampling of the electric signal provided by a signal source S which is variable between a first reference voltage (0 Volt) and a second reference voltage (VREF, reference voltage of the converter). The sampling network RCM results to be further coupled to an A/D converter CAD, also of a known type.
In some critical applications, for example, if the signal source S has to “see” a high impedance (for example, above 1 Giga-Ohm), it is necessary, as illustrated in FIG. 2, to modify the A/D conversion system 100 by adding a following device 200 (also known by the name of buffer device or, simply, buffer) interposed between the signal source S and the sampling network RCM for driving the same sampling network RCM to the aim of ensuring an infinite input impedance to the A/D converter CAD.
The buffer device 200, beside the high input impedance (which is, in theory, infinite), requires such an operating band as not to limit the frequencies of the input signal, and such a power supply rejection ratio PSRR as to drive the capacitive input stage RCM so as not to degrade the A/D converter CAD performance.
With reference to FIG. 3, a first buffer device 201 belonging to the prior art is composed of an operational amplifier OA1 with an input of the p-channel type in a non-inverting configuration with unity gain. The first buffer device of FIG. 3 is arranged to receive an input signal VI on a first input terminal of a non-inverting type, and to provide an output signal VOUT on an output terminal.
The first buffer device 201 of FIG. 3 has the drawback of resulting not usable for an input signal with a value near 0 Volts, since, as it is known to those skilled in the art, the operational amplifier OA1 output stage is not capable of operating with signals having a voltage value near 0 Volts. Furthermore, the use of the operational amplifier OA1 has the drawback of limiting the operating band of the A/D converter in which the first buffer device 201 is employed.
With reference to FIG. 4, a second buffer device 202 of a known type, alternative to that illustrated in FIG. 3, results to be composed of an operational amplifier OA2 with p-channel input in an inverting configuration with unity gain, and a transistor M1 of the p-channel MOS type.
The second buffer device 202 results to be provided with an input terminal to receive an input signal VI, and an output terminal connected to the transistor M1 gate terminal to provide a control voltage VC thereto.
The source and drain terminals of the transistor M1 are connected to a supply voltage VDD and a ground potential GND, respectively, through respective biasing resistors R. The transistor M1 source terminal represents the output terminal VOUT of the second buffer device 202.
As known to those skilled in the art, the second buffer device 202 is arranged to receive the input signal VI and to provide the output signal VOUT of a value equal to VDD-VI.
However, the second buffer device 202 has the drawback that it is highly dependant on the supply voltage VDD, which involves a PSRR value such as to cause a strong degradation of the operational amplifier OA2 performance. Furthermore, for input signals near 0 Volts, the current does not circulate through the transistor M1, thereby the second buffer device 202 stability is degraded. Furthermore, also the second buffer device 202 has a rather reduced operating band.
In FIG. 5, a third buffer device 203 of a known type (alternative to those shown in FIGS. 3 and 4, respectively) is shown. It consists of a source follower represented by a MOS transistor M2 of the p-channel type having the source terminal connected to the supply voltage VDD through a current generator IC, and the drain terminal connected to the ground potential GND. The transistor M2 gate terminal represents the input terminal of the third buffer device 203 to receive the input voltage VI. The transistor M2 source terminal represents the output terminal of the third buffer device 203 to provide in output the output voltage VOUT.
As known to those skilled in the art, the third buffer device 203 of FIG. 5 results to be arranged to receive the input voltage VI and to provide the output voltage VOUT equal to VI+|VGS|. The output voltage VOUT results to be independent from the supply voltage VDD, therefore ensuring a better PSRR value than the solutions of FIGS. 3 and 4. Furthermore, the third buffer device 203 of FIG. 5 results to be usable also with input signals near 0 Volts (or also lower), thus ensuring a higher operating band compared to the solutions described with reference to FIGS. 3 and 4.
However, the third buffer device 203 of FIG. 5 has the drawback that the voltage VGS of the MOS transistor M2 is highly dependant on process and temperature variations.